A high-speed packet switch architecture with a multichannel bandwidth allocation

A novel packet switch architecture is proposed based on a channel grouped virtual circuit (CG-VC) scheme for high-speed communication networks. The case is considered in which there are several parallel channels between two switching nodes. The CG-VC scheme allows a packet to select an available channel in such a way as to avoid congested channels using a simple, hardware-based, self-routing mechanism. As a result, the architecture provides efficient channel use and low switching delay. The performance of the proposed switch is evaluated by simulation. The results show the proposed switch significantly improves channel utilization and switching delay compared with conventional single-channel allocation transmission policies