Title :
The performance analysis of an input access scheme in a high-speed packet switch
Author :
Ali, M. K Mehmet ; Youssefi, M.
Author_Institution :
Dept. of Electr. Eng., Concordia Univ., Montreal, Que., Canada
Abstract :
The performance analysis of an input access scheme in a high-speed packet switch for broadband ISDN is presented. In this switch, each input maintains a separate queue for each of the outputs, thus there are n2 input queues in a (n×n) switch. Using synchronous operation, at most one packet per input and output will be transferred in any slot. The choice of the packets is done in a manner to maximize the throughput of the switch. Comparison of simulations with analytically derived upper and lower bounds show close to optimal throughput. The mean packet delay is also derived and its variance is bounded. This input access scheme may be implemented using neural networks
Keywords :
ISDN; broadband networks; packet switching; queueing theory; broadband ISDN; high-speed packet switch; input access scheme; input queueing; mean packet delay; neural network implementation; output queueing; performance analysis; throughput; Analytical models; Asynchronous transfer mode; B-ISDN; Delay; Fabrics; Neural networks; Packet switching; Performance analysis; Switches; Throughput;
Conference_Titel :
INFOCOM '91. Proceedings. Tenth Annual Joint Conference of the IEEE Computer and Communications Societies. Networking in the 90s., IEEE
Conference_Location :
Bal Harbour, FL
Print_ISBN :
0-87942-694-2
DOI :
10.1109/INFCOM.1991.147539
