Analysis of a packet switch with input and output buffers and speed constraints

A nonblocking N×N switch for high speed packet switching networks is considered. In practice such a switch may operate L times faster than the input/output trunk. When 1< L<N, the switch would require buffers at input as well as at output ports to keep the packet loss probability and delay within some desirable limits. An analysis is made of the performance of such a switch for an arbitrary amount of buffers per output port and speedup-factor (L). The results show that for a sizable amount of output buffers, the switch with L=3 would perform almost as good as the switch with L=N. For moderate loads, the switch with L=2 can also be implemented. The input buffers are sized according to stringent requirements of packet loss rate