DocumentCode
3553140
Title
Logic simulation system using simulation processor (SP)
Author
Saitoh, Minoru ; Iwata, Kenji ; Nakamura, Akiko ; Kakegawa, Makoto ; Masuda, Junichi ; Hamamura, Hirofumi ; Hirose, Fumiyasu ; Kawato, Nobuaki
Author_Institution
Fujitsu Ltd., Kawasaki, Japan
fYear
1988
fDate
12-15 June 1988
Firstpage
225
Lastpage
230
Abstract
A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a software system that optimizes hardware performance is discussed.<>
Keywords
VLSI; circuit analysis computing; digital simulation; integrated circuit technology; integrated logic circuits; logic CAD; 32 Mbytes; VLSI; computer design verification; hardware architecture; logic devices; software system; special-purpose logic simulation processor; Circuit simulation; Computer architecture; Condition monitoring; Discrete event simulation; Hardware; Logic circuits; Logic design; Logic devices; Signal processing; Software systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA, USA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14762
Filename
14762
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