DocumentCode
3553149
Title
Algorithm for vectorizing logic simulation and evaluation of ´VELVET´ performance
Author
Kazama, Yoshiharu ; Knoshita, Y. ; Nagafuji, Motonobu ; Murayama, Hiroshi
Author_Institution
Hitachi Ltd., Kanagawa, Japan
fYear
1988
fDate
12-15 June 1988
Firstpage
231
Lastpage
236
Abstract
A very-large-scale logic simulation engine called VELVET has been developed. VELVET is a vectorized event-driven simulator which can handle simultaneously both gate-level logic and register-transfer level structure. VELVET can process simulation jobs two orders of magnitude faster than a conventional gate-level simulator. A description is given of how to realize such high performance. An algorithm is presented for vectorizing the simulation and performance.<>
Keywords
VLSI; circuit analysis computing; digital simulation; integrated logic circuits; logic CAD; VELVET; algorithm; gate-level logic; register-transfer level structure; vectorized event-driven simulator; very-large-scale logic simulation engine; Clocks; Computational modeling; Computer simulation; Discrete event simulation; Engines; Hardware; Logic gates; Software performance; Storage automation; Supercomputers;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA, USA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14763
Filename
14763
Link To Document