Short channel MOS transistors for integrated logic circuits

This paper describes the results of an investigation into the feasibility of MOS transistors of 1-µm channel length, for integrated logic circuits. It is estimated that their use Would improve packing density by up to a factor of 25 over that achieved by current technology. An additional advantage would be increased operating speed. Assuming that the overlap capacitances of the device are correspondingly reduced, a speed improvement of up to 10 times is estimated.