Ion implantation for junction field effect transistors compatible with integrated circuits

The ability to use junction field effect transistors in integrated circuits simplifies circuit design. This paper describes the techniques used in fabricating p-channel junction field effect transistors (J-FET) in an integrated circuit, using ion implantation and standard IC processing. This circuit contains resistors, transistors and three J-FETs on the same chip. The J-FETs are used as constant current sources and have a pinch-off voltage of less than 2 volts and an IDSSof ∼ 1 ma. The J-FETs are formed by ion implanting 5 × 10¹²/cm²B⁺at 100 keV, using SiO2as a mask to define the p-region which eventually becomes the channel region. The n-type gate is formed at the same time as the emitters of the transistors. The resultant circuits are characterized by a uniform J-FET pinch-off voltage and IDSS, reflecting the control associated with ion implantation.