High performance pedestal transistor for subnanosecond logic

Performance improvement in high-speed bipolar transistors has followed obvious monotonic trends, limited by the available fabrication art: narrower emitters, smaller areas, narrower bases, the heaviest possible base doping, and, more recently, the square-like arsenic emitter profile. In establishing a well-defined, heavily doped narrow base, the collector doping is increased or, more conveniently, the base diffusion is run into a shallow buried layer. In addition to defining the short base, the heavily doped collector minimizes the Kirk effect, which appears at the high current densities used. When a heavily doped base meets a heavily doped buried layer, a large junction capacitance per unit area results. The actual base diffusion area is an order of magnitude greater than the active emitter area in typical double-base stripe, single-emitter stripe designs. Hence the proposed transistor uses a structure in which a pedestal of high doping level (10¹⁷-10¹⁸cm^-3) projects upward from the buried layer under the active emitter area only. The epitaxy is doped very lightly ( cm^-3) so that the high capacitance per unit area contributing to CCBappears only where it is unavoidable. Such lightly doped epitaxy helps to reduce collector-to-isolation capacitance, in spite of a slightly larger collector-isolation junction area. Multicircuit chips incorporating this device have been made by using two successive epitaxial depositions. After the first deposition, diffusions are made for isolation walls and for the pedestal. Out-diffusion during subsequent processing completes the isolation and brings the pedestal to the desired distance from the surface of the second epitaxial deposition The control of epitaxy required is the same as that for a conventional device, since the critical steps are the second deposition and the succeeding processes, which are nearly the same. A comparison of transistors having identical geometries (0.1 × 0.5 mil²arsenic emitter) gave the following results: Pedestal Collector Standard Collector CCB0.13pF 0.24pF CISO0.18pF 0.27pF fT(typical peak) 5GHz 4.9GHz When pedestal devices with 0.1 mil minimum oxide holes - and 0.2 mil clearances were used, loaded circuit delays of about 360 ps were found in a valid logic circuit system designed for practical application in large, fast machines. A similar model with nonpedestal transistors ran about 500 ps.