DocumentCode
3553459
Title
A VLSI DSP chip for real time iterative deconvolution
Author
Whitted, Rodney B. ; Crilly, Paul B.
Author_Institution
Dept. of Electr. & Comput. Eng., Tennessee Univ., Knoxville, TN, USA
fYear
1991
fDate
7-10 Apr 1991
Firstpage
70
Abstract
The design of a CMOS VLSI chip to perform real-time iterative deconvolution is presented. A bit-level systolic array architecture for convolution, multiplication, and addition is used to implement the circuit. A brief introduction to the iterative deconvolution problem is also given. Simulations done to data have shown that the systolic array portions of the chip will yield satisfactory throughput for millions of iterations per second
Keywords
CMOS integrated circuits; VLSI; computerised signal processing; digital signal processing chips; iterative methods; real-time systems; systolic arrays; CMOS VLSI; VLSI DSP chip; bit-level systolic array architecture; convolution; multiplication; parallel processing; real time iterative deconvolution; Circuits; Convolution; Deconvolution; Digital signal processing chips; Fourier transforms; Iterative methods; Semiconductor device measurement; Spectroscopy; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Southeastcon '91., IEEE Proceedings of
Conference_Location
Williamsburg, VA
Print_ISBN
0-7803-0033-5
Type
conf
DOI
10.1109/SECON.1991.147706
Filename
147706
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