Low noise single and dual gate D-MOS transistor

Several reports have been published on modeling the noise behavior of MOSFETs in the very-high and ultra-high frequency range. These devices showed considerable excess noise which is reflected in too high values of noise resistance Rncompared to the theoretical thermal noise limit. This report shows that at high enough frequencies the theoretical value of noise resistance (75Ω at 2 GHz) can be observed on a new kind of MOSFET called D-MOS. Measured minimum noise figures are 3.4 dB at 1 GHz and 5.1 dB at GHz for single gate devices. Noise resistance, minimum noise figure, optimum source admittance and available gain have been calculated as a function of frequency from 0.1 - 2.0 GHz for a single gate and a dual gate D-MOS structure. The results are compared to measurements, some of them made in other labs for correlation. The measurements lead to the conclusion that the thermal noise sources are sufficient to describe the noise behavior of D-MOS at high enough frequencies while at the lower frequencies the theoretical minimum noise figures could not be fully realized due to difficulties in the measurement techniques and possibly additional noise sources.