Power integrated circuits with dielectric isolation

This paper describes a method of fabricating high voltage Power Integrated Circuits using a dielectric isolation technique. The method consists of bonding silicon wafers with a silicon dioxide layer in between and forming the various circuit element by diffusion. This technique is used to fabricate a Power Integrated Circuit consisting of three transistors and six resistors with the following electrical characteristics: Collector- Base Voltage, VCBO= 450-500V @ 1 µa. Collector- Emitter Voltage, VCEO= 350-400V @ 1 µa. Collector- Base Capacitance, COB= 3pf @ 20V. Frequency - Response, fT= 60 mZE @ 10 ma., 20V. Current Gain, hFE= 50 @ 30 ma., 10V. Emitter Resistor, RE= 260 ohms. Collector Resistor, RL=11K ohms. Isolation Voltage > 1000V. High reliability is achieved by the use of field electrodes and silicon nitride junction overcoat. One of the field electrodes is kept at the collector potential and this electrode prevents surface ion build-up and interrupts induced channels, which can occur beneath the interconnecting metallization. The other electrode overlaps the Collector - Base junctions, and it has the effect of increasing the voltage capability by reducing the radius effect. The silicon nitride overcoat prevents the migration of ionic contaminants into the passivating film.