DocumentCode :
3553581
Title :
Fault tolerant digital system design
Author :
Subbarao, Wunnava V.
Author_Institution :
Dept. of Electr. & Comput. Eng., Florida Int. Univ., Miami, FL, USA
fYear :
1991
fDate :
7-10 Apr 1991
Firstpage :
124
Abstract :
Fault-tolerant design concepts, such as self purging, sift-out modular redundancy, overlapping parity, and cyclic duplication coding, are presented. In most of these methods, fault location can be identified and even possibly be isolated or corrected. Practical case studies involving these methodologies are presented. In addition, methodologies to test the voter circuit for possible malfunction or fault condition are given. Such methods can fault isolate the critical points such as the voters and data routers, and thereby improve the system reliability. Practical case studies involving recompute with shifted operands (RESO) and recompute with swapped operands are also presented. These techniques will help to verify the correctness of the computed result and notify the use of possible software or internal hardware malfunction
Keywords :
digital systems; error correction; error detection; fault location; fault tolerant computing; redundancy; cyclic duplication coding; digital system design; fault location; fault tolerant design; overlapping parity; self purging; sift-out modular redundancy; system reliability; Circuit faults; Circuit testing; Digital systems; Fault diagnosis; Fault location; Fault tolerance; Fault tolerant systems; Hardware; Redundancy; Reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Southeastcon '91., IEEE Proceedings of
Conference_Location :
Williamsburg, VA
Print_ISBN :
0-7803-0033-5
Type :
conf
DOI :
10.1109/SECON.1991.147718
Filename :
147718
Link To Document :
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