Title :
Back-gate-input MOS - A new low-power logic concept
Author :
Asai, S. ; Masuhara, T. ; Nakamura, T.
Author_Institution :
Hitachi, Ltd., Kokubunji, Tokyo, Japan
Keywords :
CMOS logic circuits; Delay effects; Insulation; Inverters; Logic circuits; Logic devices; Low voltage; MOSFET circuits; Power dissipation; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1976 International
Conference_Location :
Washigton, DC, USA
DOI :
10.1109/IEDM.1976.189014
