Utilization of special architectures in support of parallel discrete event simulation

The authors describe a project which is intended as a prototype study to demonstrate the effectiveness, as measured by execution speedup, of running parallel simulations on newly available high-performance but relatively low-cost multiple-processor architectures. The authors focus on performance problems related to the use of discrete event simulation as a tool for development of system designs, and they discuss important constraints in its use in this area. They briefly survey the high-performance architectures which can be used to speed up simulations, as well as the relationship of parallel simulation to general distributed systems issues, and they describe the model being implemented to evaluate the effectiveness of the architecture and processor synchronization technique that have been chosen