Dielectric isolation using shallow oxide and polycrystalline silicon

Previous work with polycrystalline isolation was limited in density by enhanced diffusion which precluded walled emitter geometries. Oxide isolation schemes are limited in depth by loss of planarity due to oxide bumps and resultant degradation in photolithographic definitions. A technique has been developed which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of proriding deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means. This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n-epi islands surrounded by 5 × 10⁵ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide bump at the nitride mask was typically 3000 Å and the epipoly step height was as small as 2600 Å. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The speed-power product of these circuits was approximately one-half that of junction isolated circuits.