Architecture and design of a real-time parallel processor

The authors present a novel architecture and its design for a real-time parallel array processor for high-speed digital signal processing applications. The processor generates sequential output data from a stream of input data and a set of predetermined coefficients. The processor has been designed and functionally simulated by the VHSIC Hardware Description Language. The processor includes a pipelined array of multiplier-accumulator circuits which provide parallel operation to the processor. The processor does not use parallel operation for data input rates lower than the data processing rate, but the degree of parallelism is increased up to 3 for data input rates higher than the data processing rate. This increase in the degree of parallelism enhances the data throughput more than twofold over that of any of the current conventional architecture processors that are used in similar applications