DocumentCode
3554441
Title
FA-CMOS process for low power PROM with low avalanche injection voltage
Author
Fukunaga, S. ; Kyomasu, M. ; Yasuoka, A. ; Nakao, Y. ; Nakayama, M.
Author_Institution
Mitsubishi Electric Corporation, Itami, Japan
Volume
23
fYear
1977
fDate
1977
Firstpage
291
Lastpage
293
Abstract
The combination of FAMOS and CMOS processes produces a new PROM with high performance and low power. This combined process named FA-CMOS will be described. The FA-CMOS process is based on the conventional silicon gate CMOS process using the selective oxidation process (SOP) technology. It is necessary to form the avalanche injection region capable of programming with low voltage without the breakdown of N+P-junction ( N+diffusion to P-well region ). Arsenic ions are implanted to form this region and the avalanche injection voltages of less than 20 V are obtained. In addition to the above mentioned process, the double diffusion technology simplifies the formation of source-drain and isolation region. Extremely low power ( 0.6 µW/bit ) PROM was successfully fabricated using the FA-CMOS process.
Keywords
CMOS process; CMOS technology; FETs; Impurities; Isolation technology; Low voltage; Nonvolatile memory; PROM; Silicon; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1977 International
Type
conf
DOI
10.1109/IEDM.1977.189234
Filename
1479314
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