Bipolar structures for BIMOS VLSI

Recent advances in VLSI has offered many possibilities in mixing MOSFET and Bipolar integrated structures on the same chip. The purpose of this work is to study the integration of bipolar structures in BIMOS VLSI environments. More specifically bipolar structures are studied under the constraints and guidelines of a given MOS technology; e.g. the non-exsistance of a n⁺underlayer, and the high epitaxial (substrate) resistivity. A bipolar structure, based on merging a multicollector p-n-p transistor with a multiemitter n-p-n transistor is proposed. The structure takes advantage of the availability of clock signals on a MOS chip. It can be used to realise analog, logic, memory, and digital functions. Computer simulation as well as experimental results, show that the structure can perform efficiently in a wide range of BIMOS VLSI technologies.