Optimum short-channel MOS device design for high performance VLSI

Modeling of double-boron implanted devices with channel length down to 1 µ m is described. An optimum choice of device and process parameters reduces the channel length sensitivity of threshold voltage from 0.1v/µm using single channel implant to 0.05v/µm and a corresponding punch-through sensitivity reduction from 7v/µm to 1.5v/µm. Both are measured at a channel length of 2.5µm and with a substrate bias of 2.5v. A new figure of merit, (speed) (density) product will also be introduced as a vehicle for identifying the speedy density and power trade off on the optimization of operating voltage.