• DocumentCode
    3554947
  • Title

    For incremental circuit analysis using extracted hierarchy

  • Author

    Beatty, Derek L. ; Bryant, Randal E.

  • Author_Institution
    Carnegie-Mellon Univ., Pittsburgh, PA, USA
  • fYear
    1988
  • fDate
    12-15 June 1988
  • Firstpage
    495
  • Lastpage
    500
  • Abstract
    The authors present an algorithm for extracting a two-level subnetwork hierarchy from flat netlists and its application to incremental circuit analysis in the COSMOS compiled switch-level simulator. Incremental operation is achieved by using the file system as a large hash table that retains information over many executions of the incremental analyzer. The hierarchy extraction algorithm computes a hash signature for each subnetwork by coloring vertices in a manner similar to wirelist-comparison programs, then identifies duplicates using standard hash-table techniques. Its application decreases the network preprocessing time for COSMOS by nearly an order of magnitude.<>
  • Keywords
    circuit analysis computing; logic CAD; COSMOS; compiled switch-level simulator; extracted hierarchy; file system; flat netlists; hash signature; hash table; hierarchy extraction algorithm; incremental circuit analysis; processing time reduction; two-level subnetwork hierarchy; wirelist-comparison programs; Analytical models; Assembly; Circuit analysis; Circuit simulation; Computational modeling; Contracts; Data mining; Integrated circuit interconnections; Permission; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
  • Conference_Location
    Anaheim, CA, USA
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-0864-1
  • Type

    conf

  • DOI
    10.1109/DAC.1988.14805
  • Filename
    14805