Abstract :
Two general classes of high voltage MOS IC´s may be defined. The first is structured around a conventional NMOS or PMOS technology and adds ion implanted extended drain regions, offset or stacked gates, or lightly doped drain regions to produce high voltage (50-300 volt) output devices. Such devices are generally operated with a grounded source, have an enclosed geometry, are relatively high on-resistance, and have found some application primarily in display driving. A second, more flexible technology is structured around lateral DMOS devices similar to the discrete power FET devices now widely available commercially. This technology generally uses N-epitaxial layers on P-substrates, junction isolation, and is compatible with high voltage PMOS and N channel DMOS devices, and low voltage logic devices. This paper will primarily address the latter class of circuits and will consider practical problems of high voltage device design, power dissipation limitations, parasitic surface and bulk devices, and approaches to level shifting low level logic inputs to high voltages.
