Development of a poly-gate NMOS process for research and teaching

An integrated circuit fabrication facility has been developed at the University of Florida which is suitable for undergraduate laboratories, research in process technology, and studies in DFM (design for manufacturability). The NMOS process described represents the first step toward the long-range goal of developing a CMOS technology. The design goals for the University of Florida NMOS (UF NMOS) process were to check the performance limits of the fabrication facilities and to develop a process flow which could be integrated into a one semester undergraduate laboratory. Processing capabilities include ion implantation and low-pressure chemical vapor deposition (LPCVD) of polysilicon and silicon dioxide. The availability of these processes allows design of an all-implanted technology including threshold-adjustment implants and polysilicon gates with a self-aligned MOS structure. The process description is given. Process design tools and layout tools are described. Testing procedures are outlined, and the laboratory implementation is discussed. Measured data flow from NMOS devices are included