DocumentCode
3555173
Title
Comparison of bulk silicon and SOS for VLSI CMOS
Author
Aitken, A.
Author_Institution
Mitel Semiconductor, Quebec, Canada
Volume
26
fYear
1980
fDate
1980
Firstpage
244
Lastpage
247
Abstract
Results will be discussed which indicate that both 2um bulk silicon and SOS/CMOS technologies have potential for nanosecond gate delays. The potential reduction in performance of SOS devices due to the floating substrate will be discussed. The analogue capability of present generation CMOS will be described as it can be very efficiently interfaced on-chip with high speed digital circuitry for combined analogue-digital applications.
Keywords
CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS process; CMOS technology; Delay; Parasitic capacitance; Silicon; Substrates; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1980 International
Type
conf
DOI
10.1109/IEDM.1980.189805
Filename
1481248
Link To Document