SOS/CMOS as a high performance LSI device

To realize a high performance LSI, devices used should satisfy the following requirements; 1) High speed operation, 2)-Low power consumption, 3) Easy designability and 4) Higher integration capability. SOS/CMOS has been examined both experimentally and theoretically for these aspects. Ideal CMOS operation with τpd∼100 psec with P.τ∼0.1pJ/action is obtained. 1 GHz operation is confirmed on 1/16 frequency dividers. Using the same device, maximum multiplying time, τmul∼ 25 nsec at 5 V with 1.5 mW average power at 10 MHz is obtained on a 4×4 parallel multiplier. The above result agrees with the estimation of the circuit simulation without including stray capacitance associated with wiring. The same simulation predicts τmul∼60 nsec with 200 m w at most at 16 MHz operation for a 16×16 parallel multiplier. Basic theoretical estimation predicts, for large scale integration, SOS/CMOS can operate much faster than NMOS and occupies less area than bulk CMOS.