DocumentCode
3555230
Title
Module selection for pipelined synthesis
Author
Jain, Rajiv ; Parker, Alice ; Park, Nohbyung
Author_Institution
Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear
1988
fDate
12-15 June 1988
Firstpage
542
Lastpage
547
Abstract
module selection is the process of choosing the types of modules (e.g. carry-look-ahead adder) to implement each operation (e.g. addition). The authors give a limited solution to the module selection problem for pipelined designs. A model for estimating area-time tradeoffs for pipelined designs is used to formulate the problem, and an overview of the solution technique is given. Complexities introduced by nonoptimal designs and user constraints are addressed. The results have been validated using designs generated by an automated pipeline synthesis program.<>
Keywords
circuit CAD; logic CAD; pipeline processing; CAD; area-time tradeoffs; computer aided design; module selection; nonoptimal designs; pipelined synthesis; user constraints; Character generation; Contracts; Costs; Delay; Design automation; Design optimization; Flow graphs; Pipelines; Processor scheduling;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA, USA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14813
Filename
14813
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