Fabrication and performance of InP MISFET

N-channel normally-off InP MISFETs for high-gain and high-speed application have been developed, using the following fabrication techniques: (1)Sulphur diffusion process into p- and semi-insulating InP wafers for low resistive source and drain of the n-channel FET. (2)Al2O3CVD method onto the InP substrate. (3)n-channel formation on the semi-insulating InP substrate surface. (4)A pseudo self-alignment technique for eliminating gate-drain and gate-source parasitic capacitances. Conductance and drift properties have been studied together with MIS diode capacitance measurement and AES analysis.