A new dynamic RAM cell for VLSI memories

A high density dynamic memory cell using DMOS tecnnology (DMOS cell) is proposed. A DMOS cell consists of an n-channel DMOSFET as a read gate and a p-channel MOSFET as a write gate with extensive node sharing, Since the two nDMOSFET threshold states are nondestructively detected, the readout signal voltage is almost invariant to scaling. The cell area, saved by using two polysilicon layers and triple self-aligned structure, is 50-60 % of the conventional one-transistor memory cell area. The DMOS cell was successfully fabricated, and the 1.2 V threshold shift and the 7 µA current difference per 1 µ channel width were obtained for 400 Å gate oxide test cell. The complete memory operation was confirmed with a 2×2 test cell array.