Title :
A structured custom logic-design methodology
Author :
Simone, Joseph ; Cases, Moises
Author_Institution :
IBM Corp., Boca Raton, FL, USA
Abstract :
The authors describe a custom logic-circuit design methodology for CMOS circuit technologies where design time and cost are drastically reduced by efficiently using computer-aided design tools. Also described is a hierarchical chip-design methodology where the design is logically partitioned into self-contained timetable design units
Keywords :
CMOS integrated circuits; circuit layout CAD; integrated logic circuits; logic CAD; CAD; CMOS circuit technologies; computer-aided design tools; custom logic-design methodology; hierarchical chip-design methodology; logic-circuit; self-contained timetable design units; structured methodology; Circuit synthesis; Circuit testing; Costs; Design methodology; Libraries; Logic circuits; MOS devices; Power generation economics; Very large scale integration; Wiring;
Conference_Titel :
University/Government/Industry Microelectronics Symposium, 1991. Proceedings., Ninth Biennial
Conference_Location :
Melbourne, FL
Print_ISBN :
0-7803-0109-9
DOI :
10.1109/UGIM.1991.148147
