Insulator semiconductor interfaces on InP

The electrical properties of Si3N4and SiO2layers deposited on InP substrates have been investigated via I-V, C-V, and MISFET performance curves. Layers have been deposited employing pyrolytic chemical-vapor deposition (CVD) and plasma-enhanced CVD (PECVD) processes. The results indicate that the amount of surface potential variation which can be achieved is critically dependent on the manner in which the native oxide is allowed to form prior to depositing the insulating layer. Surfaces prepared using etches such as Br-methanol or aqueous HF typically allow a surface potential variation of 0.4 volt. This can be increased to > 1 volt by employing wet-etching steps containing strong reducing agents or by in Situ hydrogen annealing of the InP prior to insulator deposition.