Leakage current in high density CCD memory structures

Measurements of leakage currents in a Series-Parallel-Series Charge Coupled Device memory will be discussed. Advanced MOS processing has strongly reduced the depletion layer generated leakage current and now diffusion of minority carriers from the bulk has become the dominant leakage contribution. A simple analytical model, taking into account the substrate parameters and the geometry of the structure, describes the experiments very well. Memory structures made on PP⁺-epitaxial material have smaller leakage currents and particularly the lateral in flow of electrons generated outside the active area is severely suppressed. A fundamental lower limit of the leakage current from a P⁺substrate will be given.