DocumentCode
3555734
Title
An isolation technology for high performance bipolar memories - IOP-II
Author
Goto, H. ; Takada, T. ; Abe, R. ; Kawabe, Y. ; Oami, K. ; Tanaka, M.
Author_Institution
Fujitsu Limited, Kawasaki, Kanagawa, Japan
fYear
1982
fDate
13-15 Dec. 1982
Firstpage
58
Lastpage
61
Abstract
An isolation technology for high performance bipolar memories has been developed. This process is called IOP-II (Isolation with Oxide and Poly-silicon), which uses steep silicon U-groove for isolation instead of conventional IOP´s V-groove. In order to investigate the applicability of this technology, a conventional 1 K-bit ECL RAM is scaled down at ratios of 0.8, 0.7 and 0.6 using IOP-II. They show good isolation characteristics and improved access times of 5.8ns, 4.8ns and 4.4ns, respectively, while that of conventional one is 7.4ns. IOP-II has made it possible to develop a high speed and density 16 K-bit RAM with 15ns access time. A 3-µm wide and 5-µm deep isolation is used. One bit memory cell size is 750µm and minimum emitter size 1.5×3µm2.
Keywords
Breakdown voltage; Epitaxial layers; Isolation technology; MOS integrated circuits; Random access memory; Read-write memory; Rough surfaces; Silicon; Surface roughness; Surface topography;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1982 International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/IEDM.1982.190211
Filename
1482745
Link To Document