Vertical DMOS power field-effect transistors optimized for high-speed operation

The optimization of planar vertical DMOS FETs for high-speed switching and amplification is discussed. Design considerations for a high-voltage device capable of sub-nanosecond switching are presented, and device layout and fabrication requirements for such a device are discussed. The fabrication sequence used to produce a high-speed vertical DMOS FET is then reviewed. Key features of the process include self-aligned polysilicon gates, fully implanted junctions, floating diffused guard rings, and gold-based metallization. The significant electrical characteristics of devices built with this process include drain-source breakdown (BVDSS) > 100 volts and common-source cutoff frequency (fco)= 2 GHz. Modelling of the dc and ac characteristics of short-channel DMOS devices is examined. Device performance in a test circuit shows that planar vertical DMOS is a good candidate for high-speed, high-voltage switching.