A statistical modeling approach for simulation of MOS VLSI circuit designs

Previous modeling publications have emphasized the model accuracy with respect to a few devices. However for VLSI circuit designs with transistors of dimension 1.3um, the statistical distribution of the transistors under normal process variations is as important as the ability to predict any one transistor´s behavior. An approach is described which obtains statistical information about DC MOSFET model parameters and device operation measurements. This information is obtained from measurments taken on similarly processed wafers from one production line. Key ingredients of this approach are the MOSFET model and test chip, automatic parameter extraction algorithms, and statistical analysis routine.