DocumentCode :
3555857
Title :
Characterization of CMOS latch-up
Author :
Huang, C.C. ; Hartranft, M.D. ; Pu, N.F. ; Yue, C. ; Rahn, C. ; Schrankler, J. ; Kirchner, G.D. ; Hampton, F.L. ; Hendrickson, T.E.
Author_Institution :
Honeywell Inc., Plymouth, Minnesota
Volume :
28
fYear :
1982
fDate :
1982
Firstpage :
454
Lastpage :
457
Abstract :
The purpose of the work was to characterize the latch-up in an N-well CMOS process with minimum channel length of 1.25 
m. Structures including SCRs, buffers, inverters, and input protections were characterized. Latch-up susceptibility is reduced for P-epi on P+substrate, starting material of low resistivity, guard band structure, relaxed layout spacings, deeper N-well, and shallower source-drain diffusion.
m. Structures including SCRs, buffers, inverters, and input protections were characterized. Latch-up susceptibility is reduced for P-epi on P+substrate, starting material of low resistivity, guard band structure, relaxed layout spacings, deeper N-well, and shallower source-drain diffusion.Keywords :
Bipolar transistors; CMOS process; Contact resistance; Electric resistance; Inverters; Power supplies; Protection; Road transportation; Testing; Thyristors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1982 International
Type :
conf
DOI :
10.1109/IEDM.1982.190323
Filename :
1482857
Link To Document :
