CMOS Latch-up elimination using Schottky barrier PMOS

A common failure mechanism in bulk CMOS integrated circuits is due to latch-up of the parasitic SCR structure. Using Schottky barrier junctions for the source and drain of the P channel transistors eliminates the PNPN structure. A technology utilizing platinum-silicide P channel source and drain and ion implanted N channel source and drain was realized demonstrating latch-up resistance without many sacrifices inherent with other methods. Anomalies in the P-MOSFET characteristics are reported and discussed.