A reduced size CMOS SRAM cell structure with two-level Al interconnection

A reduced size full CMOS SRAM cell structure having three Al wiring pitches, instead of conventional five Al wiring pitches, has been demonstrated experimentally by using an advanced two-level Al interconnect technology. A cell size measuring (=269 m²), which is at least less than 70% of the conventional five pitch cell\´s size, has been realized. In order to investigate various technical issues relating to the CMOS SRAM with this new cell structure, a 1 Kb CMOS SRAM was fabricated, and its device operation characteristics were examined. Access time of less than 25 ns, and standby current of less than 1 nA, have been achieved with the SRAM. With this cell structure, cell area of 64 Kb CMOS SRAM has been estimated to be 17.7 mm². Considerable speed improvement is also expected using this cell structure.