Multi-dimensional simulation of VLSI wiring capacitance

Accurate prediction of device current and the capacitance to be driven by that current is key to the design of FET logic and dynamic RAM circuits. This paper describes the application of two- and three-dimensional, finite-element simulation to estimate capacitance in VLSI structures. The measured total and coupling capacitances of narrow and closely-spaced lines agree with two-dimensional simulation results for an FET technology with a minimum feature size of 1.25 microns and two metal wiring levels. The capacitance of a second-metal line crossing a first-metal line is predicted with the three-dimensional model and found to be twice that estimated by two-dimensional models. Adjacent line coupling is shown to be a significant signal detractor in dynamic RAMs with closely-spaced, metal or diffused bit lines.