• DocumentCode
    3555897
  • Title

    4 × 4 bit GaAs DCFL parallel multiplier

  • Author

    Toyoda, N. ; Terada, T. ; Kanazawa, K. ; Shimizu, S. ; Yamada, H. ; Hojo, A.

  • Author_Institution
    Toshiba Corporation, Kawasaki, Japan
  • fYear
    1982
  • fDate
    13-15 Dec. 1982
  • Firstpage
    598
  • Lastpage
    601
  • Abstract
    A 4×4 bit GaAs DCFL parallel multiplier (1.7 × 1.9 mm2), which integrates 187 E-FETs and 87 D-FETs, has been fabricated. The array architecture with the "carry-save" algolithm was selected in the multiplier circuit design. Full and half adders were implemented with AND/NOR gates which saved the total number of gates and power dissipation. Test device was fabricated by Pt buried-gate planar process. Typical multiplication time of 5.5 - 6.5 ns was achieved at power dissipation of 39 mW using 1.4- \\\\mu m gate FETs.
  • Keywords
    Atmosphere; Circuit testing; Delay effects; Delay estimation; FETs; Frequency estimation; Gallium arsenide; Propagation delay; Threshold voltage; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1982 International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/IEDM.1982.190363
  • Filename
    1482897
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3555897