DocumentCode :
3555898
Title :
Capability of GaAs DCFL for high-speed gate array
Author :
Toyoda, N. ; Terada, T. ; Mochizuki, M. ; Kanazawa, K. ; Mizoguchi, T. ; Hojo, A.
Author_Institution :
Toshiba Corporation, Kawasaki, Japan
Volume :
28
fYear :
1982
fDate :
1982
Firstpage :
602
Lastpage :
605
Abstract :
Gallium-arsenide DCFL gate array (4.29 × 4.46 mm2) with 500 3-INPUT NOR gates was fabricated by Pt buried-gate planar process. The delay time was 160 ps under unloaded condition at power dissipation of 0.50 mW/gate for 1.7- 
m gate device. The delay time increased linearly with fan-out, interconnection line length and cross-over number at rates of 70 ps/fan-out, 100 ps/ mm and 4.5 ps/cross-over, respectively. Circuit simulation based on the experimental results projects that the gate delay time of 150 - 200 ps under actual loading condtition can be achieved in GaAs DCFL gate array LSI using 0.5- m gate FETs.
m gate device. The delay time increased linearly with fan-out, interconnection line length and cross-over number at rates of 70 ps/fan-out, 100 ps/ mm and 4.5 ps/cross-over, respectively. Circuit simulation based on the experimental results projects that the gate delay time of 150 - 200 ps under actual loading condtition can be achieved in GaAs DCFL gate array LSI using 0.5- m gate FETs.Keywords :
Circuit testing; Delay effects; FETs; Gallium arsenide; Insulation life; Integrated circuit interconnections; Power dissipation; Power supplies; Propagation delay; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1982 International
Type :
conf
DOI :
10.1109/IEDM.1982.190364
Filename :
1482898
Link To Document :
