Capability of GaAs DCFL for high-speed gate array

Gallium-arsenide DCFL gate array (4.29 × 4.46 mm²) with 500 3-INPUT NOR gates was fabricated by Pt buried-gate planar process. The delay time was 160 ps under unloaded condition at power dissipation of 0.50 mW/gate for 1.7- m gate device. The delay time increased linearly with fan-out, interconnection line length and cross-over number at rates of 70 ps/fan-out, 100 ps/ mm and 4.5 ps/cross-over, respectively. Circuit simulation based on the experimental results projects that the gate delay time of 150 - 200 ps under actual loading condtition can be achieved in GaAs DCFL gate array LSI using 0.5- m gate FETs.