A high density, high performance 1T DRAM cell

This paper describes the structure and technology of a conventional two layer poly one transistor DRAM cell with special device enhancements to optimize its density, speed, and SER for 256K and low cost 64K DRAM products. The cell storage capacitance is enhanced by using a thin dielectric of 150Å equivalent oxide thickness and a double-field oxidation process to reduce the storage capacitor bird beak (<0.2µm). A P-well on P^-substrate is used to provide a reflecting barrier to charge generated by incident alpha particles. Low metal wordline capacitance and short highly doped diffused bitline enhance the cell access time. Cell areas of 53 to 77µm²have been fabricated and tested. The technology uses parallel plate plasma etching on all layers and wafer stepper lithography on critical mask layers. This cell structure was used for the design of a 64K memory chip of 154 mils □ die area, 70 nsec access time, and <.001%/1KHr SER.