A new VLSI memory cell using capacitance coupling

A new VLSI memory cell, which offers small cell area, about 6F²(where F is the feature size), internal cell gain and high alpha-particle immunity is proposed. Since it employs capacitance coupling in a write operation, it requires only one bit line and is called a Capacitance-Coupling (CC) cell. A CC cell consists of three transistors and a capacitor, which are integrated in a small area by sharing their nodes with one another. The charge is stored in a P⁺-type diffused layer in a shallow N-type diffused layer. The P⁺-layer potential controls the readout current which flows through the N-layer. Experimental test devices having a 0.7 m deep N-layer and 0.2 m deep P⁺-layer were fabricated. The complete CC cell operation was confirmed.