Statistical modeling of submicron, shallow-junction, self-aligned bipolar transistors

Statistical modeling of submicron, shallow-junction, self-aligned bipolar transistors with an aim at optimizing the device design is presented in this paper. To predict the statistical variation of the device characteristics, a 3- dimensional distributed network representation of the device has been created by an automated model generation program. The distributed network parameters are calculated via a 2-dimensional device simulation program, which takes into account the band-gap narrowing effect as well as the Auger recombination. By varying the topological structure and the distributed network elements according to the process variational parameters, the statistical variations of the device terminal characteristics are obtained through circuit simulation. The procedure of generating the performance-oriented device lumped models from the result of the distributed network simulation is also described. Based on the performance-oriented model simulation, it is concluded that an ECL gate with a switching delay close to 100 pico-seconds can be achieved.