Title :
290 psec I2L circuits with five-fold self-alignment
Author :
Nakamura, Tohru ; Nakazato, Kazuo ; Miyazaki, Takao ; Ogirima, Mashiko ; Okabe, Takahiro ; Nagata, Minoru
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
New, high speed, self-aligned IIL structures with minimum gate delays of 290 psec/gate(fanout=1) and power delay products of 30 fJ/gate at low injector current levels with 3 µm × 3 µm collectors are demonstrated. Maximum toggle frequency in an IIL T-type flip-flop is measured at 2 mW and found to be up to 220 MHz.
Keywords :
Delay; Epitaxial layers; Fabrication; Flip-flops; Frequency measurement; Integrated circuit interconnections; Laboratories; Power dissipation; Sputter etching; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 1982 International
DOI :
10.1109/IEDM.1982.190386
