DocumentCode
3555973
Title
A simplified box (buried-oxide) isolation technology for megabit dynamic memories
Author
Shibata, T. ; Nakayama, R. ; Kurosawa, K. ; Onga, S. ; Konaka, M. ; Iizuka, H.
Author_Institution
Toshiba Corporation, Kawasaki, Japan
Volume
29
fYear
1983
fDate
1983
Firstpage
27
Lastpage
30
Abstract
A simplified version of BOX isolation technology is described. The new process has been greatly simplified over the original BOX by introducing an additional non-critical masking step. The body effect observed in narrow channel devices is reduced in the new structure. The capacitance measurement on diffused junctions in BOX structure shows smaller contributions from diode perimeter as compared to LOCOS structure. Hot electron reliability of small geometry MOSFETs has been also studied and the results are presented and discussed.
Keywords
Capacitance measurement; Diodes; Electrons; Etching; Isolation technology; Planarization; Plasma applications; Research and development; Resists; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1983 International
Type
conf
DOI
10.1109/IEDM.1983.190432
Filename
1483557
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