CMOS technology using SEG isolation technique

An advanced bulk CMOS process has been developed using SEG (Selective Epitaxial Growth) isolation technique and high impurity concentration substrate, in order to suppress latch-up phenomenon. CMOS devices are fabricated on epitiaxial layer, which is selectively grown over p-type silicon substrate surrounded by a 2 µm thick SiO2insulator, using a reduced pressure SiH2Cl2-H2-HCl system. P-channel devices are formed in an n-well, having 3 µm depth. The gate oxide is 20 nm thick. 400 nm thick phosphorus-doped polysilicon is used as a gate electrode. The transition region for autodoping from p⁺- substrate to the epitaxial layer is less than 1 µm. This isolation combined with low resistivity substrate is effective to reduce latch-up for CMOS circuits. Submicron gate CMOS operation is confirmed using SEG isolation technique.