• DocumentCode
    3555979
  • Title

    Advanced VIST device technology

  • Author

    Takemoto, T. ; Kawakita, K. ; Sakai, H. ; Komeda, T.

  • Author_Institution
    Matsushita Electric Industrial Co., Ltd., Osaka, Japan
  • Volume
    29
  • fYear
    1983
  • fDate
    1983
  • Firstpage
    51
  • Lastpage
    54
  • Abstract
    VIST1)(Vertically Isolated Self-aligned Transistor) Technology and its application to ICs and LSIs are presented. With a walled emitter structure, reduction of the emitter-collector leakage of the VIST, consisting of a bird´s beak-free oxide-isolated structure and an inactive base (low ρ) self-aligned to the polysilicon emitter, has been made possible. E-C leakage current was measured on a fabricated bipolar integrated circuit array containing one hundred elements/chip. It was found that the thicker the side wall oxide, the remarkably smaller the E-C leakage current became. These results were well corresponded to the density of defects which were observed by Sirtl etching of stripped wafers. Applicability of the VIST to actual device was investigated in a high-speed frequency divider and an 8×8 multiplier/accumulator.
  • Keywords
    Degradation; Epitaxial layers; Etching; Integrated circuit technology; Isolation technology; Leakage current; Oxidation; Silicon; Substrates; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1983 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1983.190438
  • Filename
    1483563