• DocumentCode
    3555981
  • Title

    A merged CMOS/bipolar VLSI process

  • Author

    Walczyk, Fred ; Rubinstein, Jorge

  • Author_Institution
    Digital Equipment Corporation, Hudson, Ma.
  • Volume
    29
  • fYear
    1983
  • fDate
    1983
  • Firstpage
    59
  • Lastpage
    62
  • Abstract
    Presented are the results of a merged CMOS/bipolar process used to implement circuit structures using both fully isolated bipolar transistors with low collector series resistance and CMOS transistors. Latch-up suppression and effective bipolar performance are simultaneously achieved by the combined use of an n+ buried layer, epitaxial processing and a tailored base ion implant. A merged CMOS/bipolar buffer circuit is described and measured results are shown.
  • Keywords
    Bipolar transistor circuits; Bipolar transistors; CMOS digital integrated circuits; CMOS process; Electrical resistance measurement; Implants; Integrated circuit measurements; Resists; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1983 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1983.190440
  • Filename
    1483565
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3555981