DocumentCode :
3555983
Title :
Scaling of SOI/PMOS transistors
Author :
Singh, H.J. ; Saraswat, K.C. ; Shott, J.D. ; McVittie, J.P. ; Meindl, J.D.
Author_Institution :
Stanford University, Stanford, CA
Volume :
29
fYear :
1983
fDate :
1983
Firstpage :
67
Lastpage :
70
Abstract :
This paper reports results from a study including the weak inversion behaviour of P-channel MOS transistors fabricated in polycrystalline silicon. The devices have a wide range of channel dopings, with channel lengths and widths down to 1.25 microns. The use of very thin polysilicon enables the gate to modulate the channel conductivity of devices in fine-grain polysilicon with gate voltage excursions of under five volts. The devices have a slow turn-on and exhibit an extended weak-inversion region. Weak-inversion currents increase with applied drain voltages up to about 5 volts, with long channel devices also showing this phenomenon. Short-channel effects are seen as the channel length approaches 2 microns and are mitigated by using a higher channel doping. Device currents drop sharply below a channel width of 2 microns, although the narrow-width effect is not as pronounced as the short-channel effects.
Keywords :
Aluminum; Annealing; Etching; Implants; MOSFETs; Plasma applications; Plasma devices; Plasma sources; Silicon; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1983 International
Type :
conf
DOI :
10.1109/IEDM.1983.190442
Filename :
1483567
Link To Document :
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