Title :
SMART: tools and methods for synthesis of VLSI chips with processor architecture
Author :
Bergstraesser, T. ; Gessner, J. ; Hafner, K. ; Wallstab, S.
Author_Institution :
Siemens AG, Munich, West Germany
Abstract :
A design environment supporting processor synthesis in data-path style is presented. The programming model of a processor described in Common Lisp is transformed into a hardware structure by tools integrated into this environment. The generation of alternative designs is supported by the interactive graphical manipulation of behaviour and hardware structure representations and their correspondences. The synthesis procedure is explained using an example.<>
Keywords :
VLSI; circuit CAD; logic CAD; CAD; Common Lisp; SMART; VLSI chips; behaviour structure-representation; data-path style; design environment; hardware structure; interactive graphical manipulation; logic design; processor architecture; processor synthesis; programming model; Automatic testing; Circuit synthesis; Circuit testing; Data structures; Hardware; Information technology; Integrated circuit synthesis; Process design; Production; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14836
