Semiconductor chip design constraints imposed by package limitations

The semiconductor package must provide electrical contact, mechanical support, and protection as well as providing a path for the dissipated heat to flow. How well the package performs these functions is often an economic compromise. To select the lowest cost packaging approach it must be understood how this choice constrains the semi conductor chip, particularly the chip area. Em phasis is placed on the package/chip trade-offs for power semiconductors. Included are forward drop limitations voltage overshoot, transient and steady state thermal impedance and package fa tigue.